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SN74GTL2107PWRTIN/a555avai12-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85


SN74GTL2107PWR ,12-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85FEATURESPW PACKAGE• Operates as a GTL–/GTL/GTL+ to LVTTL or(TOP VIEW)LVTTL to GTL–/GTL/GTL+ Transla ..
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SN74GTLP1394PW ,2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarityfeatures TI-OPC circuitry, which actively limits the overshoot caused by improperly terminatedbackp ..
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SN74GTL2107PWR
12-Bit GTL-/GTL/GTL+ To LVTTL Translator
(TOP VIEW)
VREF
1AO
2AO
EN1
11BI
11A
VCC
1BI
2BI
7BO1
7BO2
EN2
11BO
5BI
10BO2
9AO
DESCRIPTION/ORDERING
SN74GTL2107 GTL–/GTL/GTL+ TO LVTTL TRANSLATOR
Operatesa GTL–/GTL/GTL+to LVTTLor
LVTTLto Translator
Series Termination on TTL Outputof30Ω Latch-Up Doneto JEDEC Standard
JESD78
ESD Performance Tested Per JESD22 2000-V Model
(A114-B,II) 200-V Machine Model (A115-A)

The SN74GTL2107isa 12-bit set I/O and the Xeon™
processor GTL–/GTL/GTL+in dual-processor
applications. VREF GTL reference voltage
Data and inputs/outputs (LVTTL)2–6,8, 10–13, ENn onall andpin15 output.15,23 nAn Remaining outputsare open drain.9,16, 17–22, nBn Data inputs/outputs (GTL–/GTL/GTL+)24–27 GND GroundV) VCC Positive voltage
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube–40°Cto 85°C TSSOP– PW GK2107Tape and reel
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
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