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SN74GTL1655TIN/a142avai16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live Insertion
SN74GTL1655DGGRTIN/a3882avai16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live Insertion


SN74GTL1655DGGR ,16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live InsertionSCBS696I–JULY 1997–REVISED APRIL 2005FUNCTION TABLESABC(1)FUNCTIONINPUTSOUTPUTMODEBOEAB LEAB CLK AH ..
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SN74GTL1655-SN74GTL1655DGGR
16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live Insertion
FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG PACKAGE
(TOP VIEW)

1OEAB
1OEBA
VCC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
VCC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
VCC
2A8
GND
2OEAB
2OEBA
CLK
1LEAB
1LEBA
VERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
VCC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
VREF
2B6
GND
2B7
2B8
BIAS VCC
2LEAB
2LEBA
The user has the flexibilityof using this deviceat either GTL (VTT= 1.2V and VREF= 0.8V)or the preferred Memberof the Instruments Widebus™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operationin
Transparent, Latched,or Clocked Modes
OEC™ Circuitry Signal Integrity and
Reduces Electromagnetic Interference
Translates Between GTL/GTL+ Signal Level
and LVTTL Logic
High-Drive (100 Low-Output-Impedance
(12
Ω) Bus Transceiver(B Port) Edge-Rate-Control Input Configures the
B-Port Output Rise and Fall Times
Ioff, Power-Up 3-State, and BIASVCC Support
Live Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors onA
Port
DistributedVCC GND Pins Minimize
High-Speed Switching Noise

The SN74GTL1655 a high-drive (100 mA),
low-output-impedance (12Ω) 16-bit UBT™
transceiver that provides LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL translation. This
deviceis partitioned two 8-bit transceivers and
combines D-type flip-flops and D-type latchesto allow
for transparent, latched, and clocked modesof data
transfer similarto the '16501 function. This device
provides an interface between cards operating at
LVTTL logic levelsa backplane operatingat
GTL/GTL+ signal levels. Higher-speed operationisa
direct result of the output swing (<1 V),
reduced input threshold levels, and OEC™ circuitry.
The high drive is suitable for driving
double-terminated low-impedance backplanes using
incident-wave switching.
higher noise margin (VTT= 1.5V and VREF=1V) signal GTL+is the Texas Instruments derivative Gunning Transceiver Logic (GTL) JEDEC standard JESD TheB port normally operatesat GTLor levels, the A-port and control inputs are compatible with LVTTL logic levels, but are not 5-Vis the input voltagefor theB port.
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