SN74F74DR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Presetlogic diagram, each flip-flop (positive logic)PRECCLKCCQTGC C CCD TG TG TGQC C CCLR‡absolute
SN74F74N ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F74NSR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESETSDFS046A – MA ..
SN74F86 ,Quadruple 2-Input Exclusive-OR Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F86D ,Quadruple 2-Input Exclusive-OR Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F86DR ,Quadruple 2-Input Exclusive-OR GatesSN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 199 ..
SN75185 ,Multiple RS-232 Drivers And ReceiversSLLS181D–DECEMBER 1994–REVISED JANUARY 2006SCHEMATIC OF DRIVERSTo Other DriversVESDDD11.6 kΩ 9.4 kΩ ..
SN75185DB ,Multiple RS-232 Drivers And ReceiversSLLS181D–DECEMBER 1994–REVISED JANUARY 2006ORDERING INFORMATION(1)T PACKAGE ORDERABLE PART NUMBER T ..
SN75185DBR ,Multiple RS-232 Drivers And ReceiversSLLS181D–DECEMBER 1994–REVISED JANUARY 2006(1)Absolute
SN75185DBRG4 , MULTIPLE RS-232 DRIVERS AND RECEIVERS
SN75185DW ,Multiple RS-232 Drivers And ReceiversSLLS181D–DECEMBER 1994–REVISED JANUARY 2006ORDERING INFORMATION(1)T PACKAGE ORDERABLE PART NUMBER T ..
SN75185DWG4 ,Multiple RS-232 Drivers And Receivers 20-SOIC 0 to 70SLLS181D–DECEMBER 1994–REVISED JANUARY 2006SCHEMATIC OF DRIVERSTo Other DriversVESDDD11.6 kΩ 9.4 kΩ ..
SN74F74-SN74F74D-SN74F74DR-SN74F74N-SN74F74NSR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset
descriptionThese devices contain two independent positive-
edge-triggered D-type flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets
the outputs regardless of the levels of the other
inputs. When PRE and CLR are inactive (high),
data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
The SN54F74 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F74 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE†The output levels are not guaranteed to meet the
minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist
when PRE or CLR returns to its inactive (high)
level.
SN54F74... FK PACKAGE
(TOP VIEW)2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
NC – No internal connection
1CLK
1PRE
GND
2CLR
2CLK
2PRE
