SN74F377ADW ,Octal D-Type Flip-Flop With Clock Enablemaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F382N ,Arithmetic logic unit / function generator 20-PDIP 0 to 70
SN74F38D ,Quad 2-input positive-NAND buffers with open collector outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F38DR ,Quad 2-input positive-NAND buffers with open collector outputs SDFS013A − MARCH ..
SN74F38DR ,Quad 2-input positive-NAND buffers with open collector outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F38N ,Quad 2-input positive-NAND buffers with open collector outputslogic diagram (positive logic)1 131A & 1A 31Y2 2 1Y1B 1B442A 62A62Y55 2Y2B2B993A83A810 3Y10 3Y3B3B1 ..
SN75176BPSR ,Differential Bus TransceiverMaximum Ratings.. 412 Layout.... 167.2 Recommended Operating Conditions..... 412.1 Layout Guideline ..
SN75178BD ,Differential Bus Repeatersfeatures thermalshutdown for protection from line fault conditions. Thermal shutdown is designed to ..
SN75178BP ,Differential Bus Repeatersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75179AP ,Differential Driver And Receiver Pair 8-PDIP 0 to 70
SN75179B ,Differential Driver And Receiver Pairmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75179BD ,Differential Driver And Receiver Pairfeatures highinput impedance, input hysteresis for increased noise immunity, and input sensitivity ..
SN74F377A-SN74F377ADW
Octal D-Type Flip-Flop With Clock Enable
Buffer/Storage Registers
Shift Registers
Pattern Generators Buffered Common Enable Input Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
descriptionThe SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The
SN74F377A features a latched clock enable (CE) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if CE is low. Clock triggering occurs at a particular voltage level and is
not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input
signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the CE
input.
The SN74F377A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)GND
CLK
