SN74F299DWR ,Universal shift / storage registersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F299N ,Universal shift / storage registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F299N ,Universal shift / storage registers The SN54F299 is obsolete and no ..
SN74F30 ,8-input positive-NAND gateslogic diagram (positive logic)1A2B3C4D8Y5E6F11G12HPin numbers shown are for the D, J, and N package ..
SN74F30 ,8-input positive-NAND gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74F30D ,8-input positive-NAND gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN75172N ,Quadruple Differential Line Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V (see ..
SN75173 ,Quadruple Differential Line Receiverlogic diagram (positive logic)4G12G21A 31 1Y1B62A 57 2Y2B103A 119 3Y3B144A 1315 4Y4BPin numbers sho ..
SN751730 ,Triple Line Driver/ReceiverSLLS062E–MAY 1990–REVISED AUGUST 2007(1)EQUIVALENT SCHEMATICS OF DRIVER AND RECEIVERDRIVERVCC2.5 Ω1 ..
SN751730D ,Triple Line Driver/ReceiverSLLS062E–MAY 1990–REVISED AUGUST 2007ORDERING INFORMATION(1)(2)T PACKAGE ORDERABLE PART NUMBER TOP- ..
SN751730N ,Triple Line Driver/ReceiverMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNIT(2)V S ..
SN75173D ,Quadruple Differential Line Receivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74F299DW-SN74F299DWR-SN74F299N
Universal shift / storage registers
Operates With Outputs Enabled or at HighImpedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for N-Bit Word Lengths Direct Overriding Clear Applications:
− Stacked or Pushdown Registers
− Buffer Storage
− Accumulator Registers
description/ordering informationThese 8-bit universal shift/storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1, OE2) inputs can be used to
choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the
3-state outputs in a high-impedance state and
permits data that is applied on the I/O ports to
be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in
any mode. Clearing occurs when the clear (CLR) input is low. T aking either OE1 or OE2 high disables the outputs
but has no effect on clearing, shifting, or storage of data.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
