SN74F175DR ,Quadruple D-Type Flip-Flops With Clear/sc/package.FUNCTION TABLEINPUTS OUTPUTSCLR CLK D Q QL X X L HH ↑ HH LH ↑ LL HH L X Q Q0 0Please be ..
SN74F175N ,Quadruple D-Type Flip-Flops With Clearlogic diagram (positive logic)9CLK1CLR421D1D1QC13R1QTwo Identical ChannelsNot Shown13154D 1D4QC114R ..
SN74F175NSR ,Quadruple D-Type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F20 ,Dual 4-input positive-NAND gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F20D ,Dual 4-input positive-NAND gates SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES SDFS041A – MARCH 1987 – REVISED OCTOBER 1993SN54 ..
SN74F20DR ,Dual 4-input positive-NAND gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN75150D ,Dual Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75150DR ,Dual Line Driverlogic diagram (positive logic)1S1 ENSÎÎ71Y2ÎÎ2 71Y1A 1AÎÎ632A 2Y6ÎÎ3 2Y2AÎΆThis symbol is in accor ..
SN75150JG ,Dual Line Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75150P ,Dual Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN751518FT , DC Plasma Display Drivers
SN75151N ,Quadruple Differential Line Driver 20-PDIP
SN74F175D-SN74F175DR-SN74F175N-SN74F175NSR
Quadruple D-Type Flip-Flops With Clear
– Shift Registers
– Pattern Generators
descriptionThis positive-edge-triggered flip-flop utilizes TTL
circuitry to implement D-type flip-flop logic with a
direct clear (CLR) input. Information at the data
(D) inputs meeting setup-time requirements is
transferred to outputs on the positive-going edge
of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLEGND
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
