SN74F163ADR ,Synchronous 4-Bit Binary Counterfeatures a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify theoperating m ..
SN74F163AN ,Synchronous 4-Bit Binary Counterlogic diagram (positive logic)1CLR9LOAD10ENT715ENPRCO3R14QG2A2CLK 1, 2T/C331, 3DAM13R13QG2 B1, 2T/C ..
SN74F163ANSR ,Synchronous 4-Bit Binary Counter SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS088A – MARCH 1987 – REVISED AUGUST 2001D, DB, OR N ..
SN74F169N ,Synchronous 4-Bit Up/Down Binary Counter
SN74F174A ,Hex D-Type Flip-Flop With Clearelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74F174ADR ,Hex D-Type Flip-Flop With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN75146D , DUAL DIFFERENTIAL LINE RECEIVER
SN75150 ,Dual Line Driverlogic diagram (positive logic)1S1 ENSÎÎ71Y2ÎÎ2 71Y1A 1AÎÎ632A 2Y6ÎÎ3 2Y2AÎΆThis symbol is in accor ..
SN75150D ,Dual Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75150DR ,Dual Line Driverlogic diagram (positive logic)1S1 ENSÎÎ71Y2ÎÎ2 71Y1A 1AÎÎ632A 2Y6ÎÎ3 2Y2AÎΆThis symbol is in accor ..
SN75150JG ,Dual Line Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75150P ,Dual Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F163A-SN74F163ADR-SN74F163AN-SN74F163ANSR
Synchronous 4-Bit Binary Counter
descriptionThis synchronous, presettable, 4-bit binary
counter has internal carry look-ahead circuitry
for use in high-speed counting designs.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop outputs
to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
