SN74F161AD ,Synchronous 4-Bit Binary Counterlogic diagram (positive logic)1CLR9LOAD10ENT157RCOENPR14QG2 A2CLK 1, 2T/C33A1, 3DM1R13QG2 B1, 2T/C3 ..
SN74F161ADR ,Synchronous 4-Bit Binary Counter SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001D, DB, OR N ..
SN74F161AN ,Synchronous 4-Bit Binary Counter/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74F161AN ,Synchronous 4-Bit Binary Counterfeatures a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify theoperating m ..
SN74F161ANSR ,Synchronous 4-Bit Binary Counter/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74F163A ,Synchronous 4-Bit Binary Counter/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN75138NSR ,Quadruple Bus Transceivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75140JG ,Dual Line Receiverlogic diagram (positive logic)2COMSTRB11OUT31LINE6COMREF72OUT52LINEschematic (each receiver)VCC1500 ..
SN75140JG ,Dual Line Receivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75140P ,Dual Line Receivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75140PS , DUAL LINE RECEIVER
SN75140PSR ,Dual Line Receivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74F161A-SN74F161AD-SN74F161ADR-SN74F161AN-SN74F161ANSR
Synchronous 4-Bit Binary Counter
descriptionThis synchronous, presettable, 4-bit binary
counter has internal carry look-ahead circuitry
for use in high-speed counting designs.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop
outputs to low, regardless of the levels of CLK, LOAD, ENP , and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
