SN74F112DR ,Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F112N ,Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F112NSR ,Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F112NSRE4 ,Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-SO 0 to 70maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F11D ,Triple 3-input positive-AND gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F11DR ,Triple 3-input positive-AND gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN75115N ,Dual Differential Line Receivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75115NSR ,Dual Differential Line Receiver SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS072D – SEPTEMBER 1973 – REVISED MAY 1998SN55115 . ..
SN75116 ,Differential Line Transreceivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V (see ..
SN75116N ,Differential Line Transreceiverfeatures of the SN75117 Driver Output Internally Connected toReceiver Input The SN75118 is an ..
SN75116NSR ,Differential Line Transreceiverlogic diagram (positive logic)logic symbol‡’116‡’116 and SN75118& 4DYP1313 3DE EN DYS DE14 1 4DA D ..
SN751177 ,Dual Differential Driver/Receiver Pairsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74F112-SN74F112DR-SN74F112N-SN74F112NSR-SN74F112NSRE4
Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset
SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 D OR N PACKAGE • Package Options Include Plastic (TOP VIEW) Small-Outline Packages and Standard Plastic 300-mil DIPs 1CLK 1 16 V CC 1CLR description 1K 2 15 1J 3 14 2CLR The SN74F112 contains two independent J-K 4 13 2CLK 1PRE negative-edge-triggered flip-flops. A low level at 5 12 1Q 2K the preset (PRE) or clear (CLR) inputs sets or 6 11 2J 1Q resets the outputs regardless of the levels of the 7 10 2Q 2PRE other inputs. When PRE and CLR are inactive 8 9 2Q GND (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H † † L LX X X H H H H ↓ LL Q Q 0 0 H H ↓ HL H L H H ↓ LHL H H H ↓ H H Toggle H H H X X Q Q 0 0 † The output levels in this configuration are not guaranteed to meet the minimum levels for V . Furthermore, this OH configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. Copyright 1993, PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2–1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
