SN74F109DR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F109N ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F10D ,Triple 3-input positive-NAND gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74F10DR ,Triple 3-input positive-NAND gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F10N ,Triple 3-input positive-NAND gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F10NSR ,Triple 3-input positive-NAND gateslogic diagram, each gate (positive logic)1B1Y131C3 A2AY4 B62B2Y5 C2C93A1083B3Y113C†This symbol is i ..
SN75113N ,Dual Differential Line Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75113NSR ,Dual Differential Line DriverSN55113, SN75113DUAL DIFFERENTIAL LINE DRIVERSSLLS070C − SEPTEMBER 1973 − REVISED MARCH 1997SN55113 ..
SN75113NSR ,Dual Differential Line Driverfeatures of the SN55114 andSN75114 line drivers with the added feature ofdriver output controls. In ..
SN75113NSR ,Dual Differential Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75114D ,Dual Differential Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75114N ,Dual Differential Line Driver SN55114, SN75114 DUAL DIFFERENTIAL LINE DRIVERS SLLS071C – SEPTEMBER 1973 – REVISED SEPTEMBER 1998 ..
SN74F109-SN74F109DR-SN74F109N
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
descriptionThese devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and trying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
The SN54F109 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F109 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration is nonstable;
that is, it will not persist when PRE or CLR returns to its
inactive (high) level.
SN54F109... FK PACKAGE
(TOP VIEW)2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
NC – No internal connection
1CLK
1PRE
GND
2CLK
2PRE
