SN74CBT34X245DBBR ,32-Bit FET Bus Switch SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001DBB PACKAGE* Member of T ..
SN74CBT3861DBQR ,10-Bit FET Bus Switch10-Jun-2014PACKAGING INFORMATIONOrderable Device Status Package Type Package Pins Package Eco Plan ..
SN74CBT3861DBQR ,10-Bit FET Bus Switch SN74CBT3861 10-BIT FET BUS SWITCH SCDS061D – APRIL 1998 – REVISED OCTOBER 2000DBQ, DGV, DW, OR PW ..
SN74CBT3861DBQR ,10-Bit FET Bus Switchelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74CBT3861DGVR , 10-BIT FET BUS SWITCH
SN74CBT3861DGVR , 10-BIT FET BUS SWITCH
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S197N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S225N ,16 x 5 asynchronous FIFO memorymaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74S22N ,Dual 4-input Positive-NAND Schmitt triggers with open collector outputs 14-PDIP 0 to 70
SN74S241J ,Octal Buffers and Line Drivers With 3-State OutputsMaximum Ratings.. 410 Power Supply Recommendations... 176.2 ESD Ratings........ 411 Layout.... 176. ..
SN74CBT34X245DBBR
32-Bit FET Bus Switch
Flow-Through Architecture Optimizes PCBLayout Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
descriptionThe SN74CBT34X245 provides 32 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as four 8-bit bus switches,
two 16-bit bus switches, or one 32-bit bus switch.
When output enable (OE) is low, the switch is on,
and port A is connected to port B. When OE is
high, the switch is open, and the high-impedance
state exists between the two ports.
This device is fully specified for partial-power-
down applications using Ioff . The Ioff circuitry
disables the outputs, preventing damaging
current backflow through the device when it is
powered down.
NC – No internal connection
1A3
1A4
1A5
1A6
1A7
1A8
GND
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
GND
3A1
3A2
3A3
3A4
3A5
3A6
3A7
3A8
GND
4A1
4A2
4A3
4A4
4A5
4A6
4A7
4A8
GND
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2OE
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
VCC
3OE
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
VCC
4OE
4B1
4B2
4B3
4B4
4B5
4B6
4B7
4B8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.