SN74CBT3384APWR ,10-Bit FET Bus SwitchSN74CBT3384A10-BIT FET BUS SWITCHSCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004DB, DBQ, DGV, DW, O ..
SN74CBT3384APWRG4 ,10-Bit FET Bus Switch 24-TSSOP -40 to 85logic diagram (positive logic)321B11A111 101B51A511OE14 152B12A122 232B52A5132OE†absolute
SN74CBT3384CDBQR ,10-Bit FET Bus Switch with -2 V Undershoot Protection SCDS132A − SEPTEMBER 200 ..
SN74CBT3384CPWR ,10-Bit FET Bus Switch with -2 V Undershoot Protectionmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT34X245DBBR ,32-Bit FET Bus Switch SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001DBB PACKAGE* Member of T ..
SN74CBT3861DBQR ,10-Bit FET Bus Switch10-Jun-2014PACKAGING INFORMATIONOrderable Device Status Package Type Package Pins Package Eco Plan ..
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S197N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S225N ,16 x 5 asynchronous FIFO memorymaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74S22N ,Dual 4-input Positive-NAND Schmitt triggers with open collector outputs 14-PDIP 0 to 70
SN74S241J ,Octal Buffers and Line Drivers With 3-State OutputsMaximum Ratings.. 410 Power Supply Recommendations... 176.2 ESD Ratings........ 411 Layout.... 176. ..
SN74CBT3384ADBLE-SN74CBT3384ADBQR-SN74CBT3384ADBQR.-SN74CBT3384ADBQRG4-SN74CBT3384ADBR-SN74CBT3384ADGVR-SN74CBT3384ADW-SN74CBT3384ADWR-SN74CBT3384APW-SN74CBT3384APWR-SN74CBT3384APWRG4
10-Bit FET Bus Switch
SN74CBT3384A
10-BIT FET BUS SWITCH
SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004
5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels
description/ordering informationThe SN74CBT3384A provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as two 5-bit switches with
separate output-enable (OE) inputs. When OE is
low, the switch is on, and port A is connected to
port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 5-bit bus switch)
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
VCC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
