SN74CBT3383CDBQR ,10-Bit FET Bus-Exchange Switches with -2 V Undershoot Protection SCDS175 − SEPTEM ..
SN74CBT3383CPW ,10-Bit FET Bus-Exchange Switches with -2 V Undershoot Protection/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBT3383DBR ,10-Bit FET Bus-Exchange SwitchesMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74CBT3383DW ,10-Bit FET Bus-Exchange SwitchesMaximum Ratings.. 411.1 Layout Guidelines.... 116.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74CBT3383DWR ,10-Bit FET Bus-Exchange SwitchesFeatures... 18.4 Device Functional Modes...... 82 Applications..... 19 Application and Implementati ..
SN74CBT3383PW ,10-Bit FET Bus-Exchange SwitchesSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74CBT3383,SN54CBT3 ..
SN74S169J ,Synchronous 4-Bit Up/Down Binary Counters 16-CDIP 0 to 70
SN74S174 ,Hex D-Type Flip-Flops With Clear
SN74S174J ,Hex D-Type Flip-Flops With Clear
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S196N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74S197N ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74CBT3383CDBQR-SN74CBT3383CPW
10-Bit FET Bus-Exchange Switches with -2 V Undershoot Protection
Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes
Loading and Signal Distortion io(OFF) = 8 pF Typical) Data and Control Inputs Provide
Undershoot Clamp Diodes Low Power ConsumptionCC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101) Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
description/ordering information
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1
GND
5A1
5B1
4B2
4A2
4A1
4B1
3B2
3A2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
