SN74CBT16211CDGVR ,24-Bit FET Bus Switch with -2 V Undershoot Protection SCDS116C − JANUARY 20 ..
SN74CBT16211CDL ,24-Bit FET Bus Switch with -2 V Undershoot Protection/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBT16212A ,24-Bit FET Bus-Exchange Switchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74CBT16212ADGG , 24-BIT FET BUS-EXCHANGE SWITCHES
SN74CBT16212ADGGR ,24-Bit FET Bus-Exchange Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBT16212ADL ,24-Bit FET Bus-Exchange Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVTZ244PWR ,3.3-V ABT Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVU04A ,Hex Inverters SCES130L − MARCH 1998 − REVISED DECEMBER 2004 2-V to 5.5-V V Operat ..
SN74LVU04AD ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVU04ADR ,Hex Inverters/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LVU04ADRG4 ,Hex Inverters 14-SOIC -40 to 85logic diagram, each inverter (positive logic)A Y†absolute
SN74LVU04ANSR ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT16211CDGVR-SN74CBT16211CDL
24-Bit FET Bus Switch with -2 V Undershoot Protection
Propagation Delay Low ON-State Resistance (ron)
Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes
Loading and Signal Distortion io(OFF) = 5.5 pF Typical) Data and Control Inputs Provide
Undershoot Clamp Diodes Low Power ConsumptionCC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101) Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
description/ordering information
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
VCC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
