SN74AVC2T45YZPR ,DUAL BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTSLogic Diagram (Positive Logic)V VCCA CCB81VCCA VCCB5DIR2A17B13A26B2V VCCA CCB4 GND(1) Pin numbers a ..
SN74AVC32T245GKER ,1.2 V to 3.6 V, 32-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputFeaturescommunication between data buses. The device1• Member of the Texas Instruments Widebus+™tra ..
SN74AVC32T245ZKER ,1.2 V to 3.6 V, 32-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputElectrical Characteristics ...... 811.2 Layout Example....... 206.6 Switching Characteristics: V = ..
SN74AVC32T245ZRLR ,32-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 96-BGA MICROSTAR JUNIOR -40 to 85Logic Diagram• Personal ElectronicsA3 H31DIR 2DIR• IndustrialA4 H41OE 2OE• EnterpriseA5 E51A1 2A1• ..
SN74AVC4T245DGVR ,4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTSFeatures... 1 8 Detailed Description........ 128.1 Overview.. 122 Applications..... 18.2 Functional
SN74AVC4T245DT ,4-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs 16-SOIC -40 to 85Logic Diagram (Positive Logic) CC CCinput is at GND, then both ports are in the high-for 1/2 of SN7 ..
SN74LVT573DWR ,3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)11OE ENOE11LE C111LE2 191D 1D 1Q3 18C1192D 2Q1Q4 1723D 3Q 1D 1D5 164D ..
SN74LVT574DBR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVT574DW ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputslogic diagram (positive logic)11OE ENOE11CLK C111CLK2 191D 1D 1Q3 18C1192D 2Q1Q4 1723D 3Q 1D 1D5 16 ..
SN74LVT574DWR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LVT574, SN74LVT5743.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS139D ..
SN74LVT574PW , 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT574PWR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LVT574, SN74LVT5743.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS139D ..
SN74AVC2T45DCTR-SN74AVC2T45DCUR-SN74AVC2T45DCURE4-SN74AVC2T45DCURG4-SN74AVC2T45DCUT-SN74AVC2T45DCUTG4-SN74AVC2T45YZPR
Dual-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs
DIR5263 8
VCCA VCCB
VCCA VCCBProduct
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Design
SN74AVC2T45SCES531L –DECEMBER 2003–REVISED MAY 2017
SN74AVC2T45 2-Bit, Dual Supply, Bus Transceiver
With Configurable Level-Shifting and Translation Features Availablein the Texas Instruments NanoFree™
Package VCC Isolation Feature:If Either VCC InputIsat
GND, Both Ports Arein the High-Impedance State Dual Supply Rail Design I/Os Are 4.6-V Over Voltage Tolerant Ioff Supports Partial-Power-Down Mode Operation Max Data Rates 500 Mbps (1.8Vto 3.3V) 320 Mbps (<1.8Vto 3.3V) 320 Mbps (Level-Shiftingto 2.5Vor 1.8V) 280 Mbps (Level-Shiftingto 1.5V) 240 Mbps (Level-Shiftingto 1.2V) Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22
Applications Smartphones Servers Desktop PCs and Notebooks Other Portable Devices
DescriptionThis 2-bit non-inverting bus transceiver uses two
separate configurable power-supply rails. TheA ports
are designedto track VCCA and accepts any supply
voltage from 1.2Vto 3.6V. TheB ports are designed track VCCB and accepts any supply voltage from
1.2Vto 3.6V. This allows for universal low-voltage
bidirectional translation and level-shifting between
any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V
voltage nodes.
The SN74AVC2T45is designed for asynchronous
communication between two data buses. The logic
levelsof the direction-control (DIR pin) input activate
either the B-port outputsor the A-port outputs. The
device transmits data from theA busto theB bus
when the B-port outputs are activated and from theB
bus to theA bus when the A-port outputs are
activated. The input circuitry on bothA andB ports
alwaysis active and must havea logic HIGHor LOW
level appliedto prevent excess leakage current on
the internal CMOS structure.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
