SN74AUP1G240YZPR ,Low-Power Single Buffer/Driver with 3-State Output 5-DSBGA -40 to 85Electrical Characteristics....... 511.2 Layout Example....... 186.6 Switching Characteristics: C = ..
SN74AUP1G32DCKR ,Low-Power Single 2-Input Positive-OR GateFeatures 2 Applications21• Available in the Ultra Small 0.64 mm Package • ATCA Solutions(DPW) with ..
SN74AUP1G32DSFR ,Low-Power Single 2-Input Positive-OR Gate 6-SON -40 to 85Electrical Characteristics....... 512.1 Layout Guidelines.... 127.6 Switching Characteristics, C = ..
SN74AUP1G32YZPR ,Low-Power Single 2-Input Positive-OR Gate 5-DSBGA -40 to 85 SCES580I–JUNE 2004–REVISED JUNE 20146 Pin Configuration and FunctionsDBV PACKAGE DCK PACKAGEDRL PA ..
SN74AUP1G34DBVR ,Low-Power Single Buffer GateElectrical Characteristics....... 512.1 Layout Guidelines.... 127.6 Switching Characteristics, C = ..
SN74AUP1G34DCKR ,Low-Power Single Buffer GateFeatures 2 Applications21• Available in the Ultra Small 0.64 mm Package • ATCA Solutions(DPW) with ..
SN74LVT16500DGGR , 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16500DGGR , 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16500DLR , 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16500DLR , 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16501 ,3.3-V ABT 18-Bit Universal Bus Transceivers With 3-State Outputs SN54LVT16501, SN74LVT16501 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS147 ..
SN74LVT16501DGGR ,3.3-V ABT 18-Bit Universal Bus Transceivers With 3-State Outputslogic diagram (positive logic)1OEAB55CLKAB2LEAB28LEBA30CLKBA27OEBA3A1 1D 54B1C1CLK1DC1CLKTo 17 Othe ..
SN74AUP1G240DBVR-SN74AUP1G240YZPR
Low-Power Single Buffer/Driver with 3-State Output
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SN74AUP1G240SCES627D –MARCH 2005–REVISED OCTOBER 2017
SN74AUP1G240 Low-Power Single Inverter With 3-State Output Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Performance Tested Per JESD22 2000-V Human-Body Model
(A114-B, ClassII) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments NanoStar™
Package Low Static-Power Consumption ICC= 0.9 µA Maximum Low Dynamic-Power Consumption Cpd= 4.2 pFat 3.3V Typical Low Input Capacitance CI= 1.5 pF Typical Low Noise– Overshoot and Undershoot
<10%of VCC Input-Disable Feature Allows Floating Input
Conditions Ioff Supports Partial Power-Down-Mode Operation Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunityat the Input Wide Operating VCC Rangeof 0.8Vto 3.6V Optimized for 3.3-V Operation 3.6-V I/O Tolerantto Support Mixed-Mode Signal
Operation tpd= 4.7ns Maximumat 3.3V Suitablefor Point-to-Point Applications
Applications Grid infrastructure Telecom Infrastructure Medical, Healthcare, and Fitness and Control
DescriptionThe AUP family is TI's premier solution to the
industry's low power needs in battery-powered
portable applications. This family assuresa very low
static and dynamic power consumption across the
entire VCC rangeof 0.8Vto 3.6V, resultingin an
increased battery life. This product also maintains
excellent signal integrity (see AUP– The Lowest-
Power Family).
This buffer/driverisa single line driver witha 3-state
output. The output is disabled when the output-
enable (OE) inputis high. This device has the input-
disable feature, which allows floating input signals. assure the high-impedance state during power up power down, OE should be tiedto VCC througha
pullup resistor; the minimum valueof the resistoris
determined by the current-sinking capability of the
driver.
NanoStar™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
