SN74AUP1G14DBVRG4 ,Low-Power Single Schmitt-Trigger Inverter 5-SOT-23 -40 to 85Features 3 DescriptionThe AUP family is TI's premier solution to the1• Latch-Up Performance Exceeds ..
SN74AUP1G14DCKR ,Low-Power Single Schmitt-Trigger InverterElectrical Characteristics....... 511.2 Layout Example....... 166.6 Switching Characteristics: C = ..
SN74AUP1G14DRLR ,Low-Power Single Schmitt-Trigger Inverter 5-SOT -40 to 85 SCES578J–JUNE 2003–REVISED SEPTEMBER 20175 Pin Configuration and FunctionsDBV PackageDCK Package5- ..
SN74AUP1G17DCKR ,Low-Power Single Schmitt-Trigger BufferFeatures 3 DescriptionThe AUP family of devices is TI's premier solution to1• Latch-Up Performance ..
SN74AUP1G17DCKRG4 ,Low-Power Single Schmitt-Trigger Buffer 5-SC70 -40 to 85 SCES579J–JUNE 2004–REVISED SEPTEMBER 20175 Pin Configuration and FunctionsDBV PackageDCK Package5- ..
SN74AUP1G17DCKT ,Low-Power Single Schmitt-Trigger BufferElectrical Characteristics....... 511.2 Layout Example....... 166.6 Switching Characteristics: C = ..
SN74LVT16245ADLR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State Outputs 48-SSOP -40 to 85 SN54LVT16245A, SN74LVT16245A 3.3-V ABT 16-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS143E – MAY 1 ..
SN74LVT16245B ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006DESCRIPTION/ORDERING INFORMATION (CONTINUED)The 'LVT162 ..
SN74LVT16245BDGGR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsFEATURESSN54LVT16245B . . . WD PACKAGE• Member of the Texas Instruments Widebus™SN74LVT16245B . . . ..
SN74LVT16245BDGVR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006(1)FUNCTION TABLE(each 8-bit section)CONTROL INPUTS OUT ..
SN74LVT16245BDL ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)2412DIR1DIR48 251OE 2OE36471A1 2A12 131B1 2B1To Seven Other Channels ..
SN74LVT16245BGQLR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSN54LVT16245B,, SN74LVT16245B3.3-V ABT 16-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
SN74AUP1G14DBVRG4-SN74AUP1G14DCKR-SN74AUP1G14DRLR
Low-Power Single Schmitt-Trigger Inverter
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SN74AUP1G14SCES578J–JUNE 2003–REVISED SEPTEMBER 2017
SN74AUP1G14 Low-Power Single Schmitt-Trigger Inverter Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Performance Tested Per JESD22 2000-V Human-Body Model
(A114-B, ClassII) 1000-V Charged-Device Model (C101) Low Static-Power Consumption
(ICC= 0.9 µA Maximum) Low Dynamic-Power Consumption
(Cpd= 4.4 pF Typicalat 3.3V) Low Input Capacitance (CI= 1.5pF Typical) Low Noise– Overshoot and Undershoot
<10%of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs Wide Operating VCC Rangeof 0.8Vto 3.6V Optimized for 3.3-V Operation 3.6-V I/O Tolerantto Support Mixed-Mode Signal
Operation tpd= 4.9ns Maximumat 3.3V
Applications AV Receivers Smartphones Blu-ray Players and Home Theaters DVD Recorders and Players Desktopor Notebook PCs Embedded PCs GPS: Personal Navigation Devices Mobile Internet Devices Portable Media Players Smoke Detectors (SSD): Enterprise
DescriptionThe AUP family is TI's premier solution to the
industry's low power needs in battery-powered
portable applications. This family assuresa very low
static and dynamic power consumption across the
entire VCC rangeof 0.8Vto 3.6V, resultingin an
increased battery life. This product also maintains
excellent signal integrity (see AUP– The Lowest-
Power Family and Excellent Signal Integrity).
This device functions as an independent gate with
Schmitt-trigger inputs, which allows for slow input
transition and better switching-noise immunityat the
input.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
(DBV, DCK, DRL, DRY, DSF, DPW, and YZP
Packages)
Logic Diagram (Positive Logic)
(YFP Package)
