SN74AUC74RGYRG4 ,Dual Positive-Edge-Triggered D-Type Flip-Flops with Clear and Preset 14-VQFN -40 to 85FEATURESRGY PACKAGE• Optimized for 1.8-V Operation and Is 3.6-V I/O(TOP VIEW)Tolerant to Support Mi ..
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SN74AUP1G00DCKR ,Low-Power Single Two-Input Positive-NAND GateFeatures 2 Applications1• ESD Performance Tested Per JESD 22 • ATCA Solutions– 2000-V Human-Body Mo ..
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SN74LVT162245ADGGR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State Outputs/sc/package.(2) Product previewGQL OR ZQL PACKAGE (1)TERMINAL ASSIGNMENTS(TOP VIEW)(56-Ball GQL/ZQL ..
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SN74LVT16240DL ,3.3-V ABT 16-Bit Buffers/Drivers With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
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SN74AUC74RGYRG4
Dual Positive-Edge-Triggered D-Type Flip-Flops with Clear and Preset
www.ti.com
FEATURES RGY PACKAGE
(TOP VIEW) 14 8
2CLR
2CLK
2PRE
1CLR
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESETSCES483A–AUGUST 2003–REVISED MARCH 2005
Optimized for 1.8-V Operation andIs 3.6-V I/O
Tolerantto Support Mixed-Mode Signal
Operation Ioff Supports Partial-Power-Down Mode
Operation Sub-1-V Operable Maxtpdof 1.8 nsat 1.8 Low Power Consumption, ±8-mA
Output Driveat Latch-Up Performance
JESD 78, ClassII ESD Protection Exceeds 2000-V Human-Body 200-V Machine Model 1000-V Charged-DeviceThis dual positive-edge-triggered specifically
for 1.65-Vto 1.95-V low levelat the the levelsof the
other inputs. When the setup time
requirementsis triggering occursa voltage level
dataat theD input the flip-flop for
higher frequencies,
This deviceis fully the outputs,
preventing damaging
MARKING–40°Cto 85°C
(1) Package drawings,at
www.ti.com/sc/package.
