SN74AUC1G79DCKR ,Single Positive-Edge-Triggered D-Type Flip-FlopFeatures 3 DescriptionThis single positive-edge-triggered D-type flip-flop is1• Latch-Up Performanc ..
SN74AUC1G79DCKRG4 ,Single Positive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 85 SCES387L–MARCH 2002–REVISED JUNE 20175 Pin Configuration and FunctionsDBV PackageDCK Package5-Pin ..
SN74AUC1G80DBVR ,Single Positive-Edge-Triggered D-Type Flip-FlopFEATURES• Available in the Texas Instruments • Low Power Consumption, 10-μA Max ICCNanoFree™ Packag ..
SN74AUC1G80DCKR ,Single Positive-Edge-Triggered D-Type Flip-FlopSCES388K–MARCH 2002–REVISED JANUARY 2007(1)Recommended Operating ConditionsMIN MAX UNITV Supply vol ..
SN74AUC1G86DBVR ,Single 2-Input Exclusive-OR GateSCES389J–MARCH 2002–REVISED NOVEMBER 2007(1)RECOMMENDED OPERATING CONDITIONSMIN MAX UNITV Supply vo ..
SN74AUC1G86DCKR ,Single 2-Input Exclusive-OR GateFEATURES2• Available in the Texas Instruments NanoFree™ • Low Power Consumption, 10-μA Max ICCPacka ..
SN74LVCU04APWR ,Hex InverterLOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC)A Y(1)Absolute
SN74LVCZ161284AGR ,19-Bit IEEE 1284 Std Bus InterfaceSCES358B–SEPTEMBER 2001–REVISED MAY 2005DESCRIPTION/ORDERING INFORMATION (CONTINUED)The power-on re ..
SN74LVCZ161284AGR ,19-Bit IEEE 1284 Std Bus InterfaceFEATURESDGG PACKAGE• Power-On Reset (POR) Prevents Printer(TOP VIEW)Errors When Printer Is Turned O ..
SN74LVCZ16244ADGGR ,16-Bit Buffer/Driver With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVCZ16245A ,16-Bit Bus Transceiver With 3-State Outputs SN74LVCZ16245A 16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTSSCES278D – JUNE 1999 – REVISED AUGUST 200 ..
SN74LVCZ16245ADGGR ,16-Bit Bus Transceiver With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AUC1G79DBVR-SN74AUC1G79DCKR-SN74AUC1G79DCKRG4
Single Positive-Edge-Triggered D-Type Flip-Flop
CLK
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SN74AUC1G79SCES387L –MARCH 2002–REVISED JUNE 2017
SN74AUC1G79 Single Positive-Edge-Triggered D-type Flip-Flop Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments NanoFree™
Package Optimized for 1.8-V Operation andIs 3.6-V I/O
Tolerantto Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Maxtpdof 1.9nsat 1.8V Low Power Consumption, 10-µA Maximum ICC ±8-mA Output Driveat 1.8V
Applications AV Receiver Audio Dock: Portable Blu-Ray Player and Home Theater Embedded PC MP3 Player/Recorder (Portable Audio) Personal Digital Assistant (PDA) Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital Solid State Drive (SSD): Client and Enterprise TV: LCD/Digital and High-Definition (HDTV) Tablet: Enterprise Video Analytics: Server Wireless Headset, Keyboard, and Mouse
DescriptionThis single positive-edge-triggered D-type flip-flopis
operationalat 0.8-Vto 2.7-V VCC, butis designed
specificallyfor 1.65-Vto 1.95-V VCC operation.
When dataat the data (D) input meets the setup time
requirement, the datais transferredto theQ output the positive-going edgeof the clock pulse. Clock
triggering occursata voltage level andis not directly
relatedto the rise timeof the clock pulse. Following
the hold-time interval, dataat theD input can be
changed without affecting the levelsat the outputs.
NanoFree™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device whenitis powered down.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
