SN74AS174NSR ,Hex D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings over operating free-air temperature range, SN54/74ALS174,†SN54/74ALS175 (unless oth ..
SN74AS175B ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings over operating free-air temperature range, SN54/74ALS174,†SN54/74ALS175 (unless oth ..
SN74AS175B ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175BHEX/QUA ..
SN74AS175BN ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear/sc/package.‡This orderable is not recommended for new designs.FUNCTION TABLE(each flip-flop)INPUTS ..
SN74AS175BNSR ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AS1808N ,Hex 2-Input AND Drivers 20-PDIP 0 to 70
SN74LVC374ADBRG4 , OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVC374ADW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsBlock Diagram... 114 Simplified Schematic 19.3 Feature Description.... 115 Revision History........ ..
SN74LVC374ADWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SCAS296O–JANUARY 1993–REVISED JULY 20146 Pin Configuration and FunctionsSN54LVC374A . . . J OR W P ..
SN74LVC374ANSR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsMaximum Ratings . 410.2 Typical Application... 127.2 Handling Ratings. 411 Power Supply Recommendat ..
SN74LVC374APW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsElectrical Characteristics table. .... 6• Added Timing Requirements table for SN74LVC374A at –40°C ..
SN74LVC374APWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsMaximum Ratings . 410.2 Typical Application... 127.2 Handling Ratings. 411 Power Supply Recommendat ..
SN74AS174-SN74AS174N-SN74AS174NSR
Hex D-Type Positive-Edge-Triggered Flip-Flops With Clear
Isolation From External Disturbances
(’AS Only)
SN54ALS175 ...J OR W PACKAGE
SN54AS175B ...J PACKAGE
SN74ALS175, SN74AS175B... D, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174 ...J OR W PACKAGE
SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D , N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174, SN54AS174... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
NC – No internal connection
CLR
GND
VCC
CLK
SN54ALS175... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
CLR
GNDCC
CLK
descriptionThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
