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SN74ALVCHR16601-SN74ALVCHR16601DL-SN74ALVCHR16601GR
18-Bit Universal Bus Transceiver With 3-State Outputs
FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GND
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
SN74ALVCHR16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS Memberof the Texas Instruments Widebus™
Family
Resistors, So External Resistors Are
Required Bus Hold on Inputs Eliminates the Need
for External Resistors Latch-Up Performance Exceeds 250 mA Per
JESD17 ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)This 18-bit universal transceiveris designed for
1.65-Vto 3.6-V VCC
The SN74ALVCHR16601 combines D-type latches
and D-type flip-flopsto allow data flowin transparent,
latched, clocked, clock-enabled modes.
Data flow in direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs. For
A-to-B data flow, the device operates in the
transparent mode LEABis high. When LEABis
low, theA dataif CLKABis heldata high low logic level. LEABis low, theA datais stored the latch/flip-flop on the low-to-high transitionof
CLKAB. When OEABis low, the outputs are active.
When OEAB high, the outputs are in the
high-impedance
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGTube ALVCHR16601Tape and reelto 85°C Tape and reel ALVCHR16601 VR601 Package drawings, packing quantities, and PCB design guidelinesare availableat
