SN74ALVCH16820DGGR ,3.3-V 10-Bit Flip-Flop with Dual Outputs and 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
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SN74LVC2G00DCURG4 , DUAL 2-INPUT POSITIVE-NAND GATE
SN74ALVCH16820DGGR
3.3-V 10-Bit Flip-Flop with Dual Outputs and 3-State Outputs
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)1OE
1Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
CLK
GND
GND
VCC
GND
D10
NC − No internal connection
Active bus-hold circuitry holds unusedor undriven inputsa valid logic state. Useof pullupor pulldown resistors
SN74ALVCH16820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS Member the Texas Instruments Widebus™
Family Bus Hold Data Inputs Eliminates the Need
for External Pullup/Pulldown ResistorsThis 10-bitis designed for 1.65-Vto 3.6-V
VCC operation.
The flip-flops of the SN74ALVCH16820 are
edge-triggered D-type flip-flops. On the positive
transition of clock (CLK) input, the device
provides trueat theQ outputs. buffered output-enable (OE) input can be usedto
place the tenin eithera normal logic state
(highor low level)or the high-impedance state. the high-impedance state, the outputs neither load
nor drive bus lines significantly. The
high-impedance state and increased drive provide the
capabilityto bus lines without need for interface pullup components. input does affect the internal operationof the
flip-flops. Old can be retainedor new data can entered while the outputs are in the
high-impedance state. ensure the state during power up power down, OE should be tiedto VCC througha
pullup resistor; the minimum valueof the resistoris
determined the current-sinking capability of the
driver.
with the bus-hold circuitryis not recommended.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGTube SN74ALVCH16820DLSSOP-DL ALVCH16820to 85°C Tape and reel SN74ALVCH16820DLR
TSSOP- DGG Tape and reel SN74ALVCH16820DGGR ALVCH16820 drawings, quantities, thermal data, symbolization, and PCB design guidelinesare availableat
