SN74ALVCH16646DGGR ,16-Bit Bus Transceiver And Register With 3-State OutputsFEATURESDGG, DGV, OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 561DIR 1 ..
SN74ALVCH16646DGGR ,16-Bit Bus Transceiver And Register With 3-State OutputsSCES032F–JULY 1995–REVISED SEPTEMBER 2004FUNCTION TABLEINPUTS DATA I/OsOPERATION OR FUNCTIONOE DIR ..
SN74ALVCH16646DL ,16-Bit Bus Transceiver And Register With 3-State OutputsSCES032F–JULY 1995–REVISED SEPTEMBER 2004OE DIR CLKAB CLKBA SAB SBA OE DIR CLKAB CLKBA SAB SBAL L X ..
SN74ALVCH16721DGGR ,3.3-V 20-Bit Flip-Flop With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH16820DGGR ,3.3-V 10-Bit Flip-Flop with Dual Outputs and 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH16821DGGR ,3.3-V 20-Bit Bus-Interface Flip-Flop with 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family11OE 56 1CLK• Bu ..
SN74LVC257APW ,Quadruple 2-Line To 1-Line Data Selector/Multiplexer With 3-State Outputs SCAS294O–JANUARY 1993–REVISED JUNE 20155 Device OptionsPART NUMBER PACKAGE BODY SIZESN74LVC257ARGY ..
SN74LVC257APWR ,Quadruple 2-Line To 1-Line Data Selector/Multiplexer With 3-State OutputsMaximum Ratings.. 512 Layout.... 137.2 ESD Ratings........ 512.1 Layout Guidelines.... 137.3 Recomm ..
SN74LVC257APWRG4 ,Quadruple 2-Line To 1-Line Data Selector/Multiplexer With 3-State Outputs 16-TSSOP -40 to 85Logic Diagram (Positive Logic)15OE1A/B21A41Y31B52A72Y62B113A93Y103B144A124Y134BPin numbers shown ar ..
SN74LVC257APWTG4 , QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
SN74LVC257ARGYR ,Quadruple 2-Line To 1-Line Data Selector/Multiplexer With 3-State OutputsTable of Contents9.1 Overview.. 101
SN74LVC257ARGYRG4 , QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
SN74ALVCH16646-SN74ALVCH16646DGGR-SN74ALVCH16646DL
16-Bit Bus Transceiver And Register With 3-State Outputs 56-TSSOP -40 to 85
FEATURES
DESCRIPTION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER Memberof the Texas Widebus™
Family EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process ESD Protection Exceeds 2000V Per
MIL-STD-883, Method Exceeds 200V
Using Machine Model= 200 pF,R=0) Latch-Up Performance Exceeds 250 mA Per
JESD17 Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil
Shrink Small-Outline Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV)This 16-bit bus transceiver and registeris designed
for 1.65-Vto 3.6-V VCC operation.
The SN74ALVCH16646 be used as two 8-bit
transceiversor one 16-bit Data on theA B bus is clocked the registers on the
low-to-high transitionof the clock (CLKAB CLKBA) input. Figure 1 illustrates the four
fundamental bus-management functions that can be
performed with the SN74ALVCH16646.
Output-enable (OE) and (DIR) inputs
are providedto control transceiver functions.In
the transceiver mode, data present at the
high-impedance port may storedin either registerin both. The select-control (SAB and SBA) inputs
can multiplex stored and (transparent mode) data. The circuitry used for select control eliminates the
typical decoding glitch thatina multiplexer during the transition between stored and real-time data. DIR
determines which bus receives data when OEis low.In the isolation (OE high),A data may be storedin
one register and/orB databe storedin the other register.
When an output function disabled, the input functionis still enabled and may be usedto store and transmit
data. Only oneof the twoAorB, canbe drivenata time. ensure the high-impedance state during power upor power down, should be tiedto VCC througha pullup
resistor; the minimum value the resistoris determinedby the current-sinking capabilityof the driver. bus-hold circuitryisto hold unusedor floating data inputsata valid logic level.is for operation from -40°Cto
