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SN74ALVCH162841TIN/a19avai20-Bit Bus-Interface D-Type Latch With 3-State Outputs


SN74ALVCH162841 ,20-Bit Bus-Interface D-Type Latch With 3-State Outputsfeatures 3-state outputs24 33 2D82Q8designed specifically for driving highly capacitive orGNDGND 25 ..
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SN74ALVCH162841
20-Bit Bus-Interface D-Type Latch With 3-State Outputs
DESCRIPTION
(TOP VIEW)

1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
SN74ALVCH162841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
Memberof Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-Ω Series
Resistors, No External Resistors Are
Required
ESD Protection Exceeds 2000V Per
MIL-STD-883, Method 3015; Exceeds 200V
Using Machine Model(C= 200 pF,R=0)
Latch-Up Exceeds 250 mA Per
JESD17
Bus Hold Data Inputs Eliminates the Need
for External Resistors
Package Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

NOTE:For tape-and-reel order entry,the DGGR packageis
abbreviated GR.
This 20-bit bus-interface D-type latchis designed for
1.65-Vto 3.6-V operation.
The SN74ALVCH162841 features 3-state outputs
designed specifically for driving highly capacitiveor
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
unidirectional drivers, and working registers.
The SN74ALVCH162841 can be used as two 10-bit
latches or one latch. The 20-bit latchisa
transparent D-type latch. The device has noninverting
data (D) inputs provides true dataatits outputs.
While the latch-enable (1LEor 2LE) inputis high, the outputsof the 10-bit latch follow the inputs. Whenis taken low, theQ outputs are
latchedat the setupat theD inputs.

buffered output-enable (1OEor 2OE) input can be used place the outputsof the corresponding 10-bit latch eithera normal logic state (highor low logic levels)or high-impedance state.In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. not the internal operationof the latches. data can be retainedor new data can be entered arein the high-impedance state. which are designedto sinkupto12 mA, include equivalent 26-Ω resistorsto reduce overshoot and
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