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SN74ALVCH162827GR ,20-Bit Buffer/Driver With 3-State OutputsFEATURESDGG, DGV, OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1OE1 1 561 ..
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SN74ALVCH162721-SN74ALVCH162721GR
3.3-V 20-Bit Flip-Flop With 3-State Outputs 56-TSSOP -40 to 85
FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)GND
VCC
GND
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
CLK
GND
VCC
GND
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
NC − No internal connection
SN74ALVCH162721 Member the Texas Instruments Widebus™
Family EPIC™ Implanted
CMOS) Process Output Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required ESD Protection Exceeds 2000V Per
MIL-STD-883, Method 3015; Exceeds 200V
Using Model(C= 200 pF,R=0) Latch-Up Performance Exceeds 250 mA Per
JESD Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors Package Include Plastic 300-mil
Shrink (DL) and Thin Shrink
Small-Outline (DGG) PackagesNOTE:For tape-and-reel order entry,the DGGR packageis
abbreviatedto GR.
This 20-bitis designed for low-voltage 1.65-V 3.6-V VCC
The 20 flip-flops of the SN74ALVCH162721 are
edge-triggered D-type flip-flops with qualified clock
storage. On positive transitionof the clock (CLK)
input, the device provides true dataat theQ outputsif
the clock-enable (CLKEN) inputis low.If CLKENis
high,no data stored. buffered (OE) input places the 20
outputsina normal logic state (high or low
level) or high-impedance state. In the
high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance
state and drive provide the capabilityto drive bus lines without interfaceor pullup components. OE
does not affect the internal operationof the flip-flops. Old data canbe retainedor new data canbe entered while
the outputsin the high-impedance state. ensure high-impedance state during power up down, OE should be tiedto VCC througha pullup
resistor; the valueof the resistoris determined the current-sinking capabilityof the driver. bus-hold circuitryis providedto hold unusedor data inputsata valid logic level. outputs, are designedto sinkupto12 mA, equivalent 26-Ω resistorsto reduce overshoot and characterizedfor operation -40°Cto 85°C.
