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SN74ALVCH162601TIN/a15avai18-Bit Universal Bus Transceiver With 3-State Outputs
SN74ALVCH162601DGGRTEXASN/a36avai18-Bit Universal Bus Transceiver With 3-State Outputs
SN74ALVCH162601DGGRTIN/a23avai18-Bit Universal Bus Transceiver With 3-State Outputs
SN74ALVCH162601GRTIN/a20avai18-Bit Universal Bus Transceiver With 3-State Outputs
SN74ALVCH162601GRN/a2000avai18-Bit Universal Bus Transceiver With 3-State Outputs


SN74ALVCH162601GR ,18-Bit Universal Bus Transceiver With 3-State OutputsMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74ALVCH162601GR ,18-Bit Universal Bus Transceiver With 3-State OutputsSCES026H–JULY 1995–REVISED AUGUST 2004(1)FUNCTION TABLEINPUTSOUTPUTBCLKENAB OEAB LEAB CLKAB AX H X ..
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SN74ALVCH162601-SN74ALVCH162601DGGR-SN74ALVCH162601GR
18-Bit Universal Bus Transceiver With 3-State Outputs
FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)

OEAB
LEAB
GND
VCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
GND
VCC
GND
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
Data flowin eachis controlledby output-enable and OEBA), latch-enable (LEAB and LEBA),
SN74ALVCH162601 UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
Memberof Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT™ (Universal Bus Transceiver) Combines
D-Type Latches and D-Type Flip-Flops for
Operationin Latched, Clocked, Clock-Enabled Modes
B-Port Outputs Have Equivalent 26-Ω Series
Resistors, So External Resistors Are
Required
ESD Protection Exceeds 2000V Per
MIL-STD-883, 3015; Exceeds 200V
Using Machine Model(C= 200 pF,R=0)
Latch-Up Performance Exceeds 250 mA Per
JESD17
Bus Hold on Inputs Eliminates the Need
for External Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline Packages

NOTE: For tape-and-reel order entry,the DGGR packageis
abbreviated
This 18-bit universal bus transceiveris designed for
1.65-Vto 3.6-V VCC operation.
The SN74ALVCH162601 combines D-type latches
and D-type flip-flopsto allow data flowin transparent,
latched, clocked, clock-enabled modes.
and clock (CLKAB and CLKBA) inputs. The clock can controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. A-to-B data flow, the device operates the transparent mode when LEABis high. When
LEABis low, the datais latchedif CLKABis heldata highor low logic level.If LEABis low, theA datais
storedin the latch/flip-flop on the low-to-high transitionof When OEABis low, the outputs are active.
When OEABis high, the outputs arein the high-impedance
Data flow forBtois similarto thatofAtoB, but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs equivalent 26-Ω series resistors overshoot and undershoot. the high-impedance state during power upor power down, OE should be tiedto VCC througha pullup minimum valueof the resistoris determinedby current-sinking capabilityof the driver.to hold unusedor floating inputsata valid logic level.to 85°C.
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