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SN74ALVCH162334DGGR-SN74ALVCH162334VR
16-Bit Universal Bus Driver With 3-State Outputs
FEATURES
DESCRIPTION
DGG, DGV, OR DL PACKAGE
(TOP VIEW)GND
VCC
GND
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
CLK
GND
VCC
GND
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
NC − No internal connection
Data flow fromAYis controlledby the output-enable (OE) The device operatesin the transparent mode
SN74ALVCH162334 Memberof Texas Instruments Widebus™
Family EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process Output Port Equivalent 26-Ω Series
Resistors, So External Resistors Are
Required Designedto With JEDEC 168-Pin and
200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000V Per
MIL-STD-883, 3015; Exceeds 200V
Using Machine Model(C= 200 pF,R=0) Latch-Up Performance Exceeds 250 mA Per
JESD17 Bus Hold on Inputs Eliminates the Need
for External Resistors Package Options Include Plastic Shrink
Small-Outline Thin Shrink Small-Outline
(DGG), and Very Small-Outline (DGV)
PackagesNOTE:For tape-and-reel order entry,the DGGR packageis
abbreviated andthe DGVR packageis abbreviated VR.
This 16-bit universal bus driveris designed for 1.65-V 3.6-VVCC operation.
when the latch-enable (LE) inputis low. When LEis high, the datais latchedif the clock (CLK) inputis heldat highor low logic level.If LEis high, theA datais stored the latch/flip-flop on the low-to-high transitionof
CLK. When OE the outputs arein the high-impedance
The output port equivalent 26-Ω series resistorsto overshoot and undershoot. ensure the high-impedance state during power upor power down, OE should be tiedtoVCC througha pullup
resistor; the minimum valueof the resistoris determinedby current-sinking capabilityof the driver.
Active bus-holdis providedto hold unusedor floating inputsata valid logic level.
The SN74ALVCH162334is characterizedfor operation fromto 85°C.
