SN74ALVC7804-25DL ,512 x 18 3.3-V asynchronous FIFO memory SN74ALVC7804 512 × 18 FIRST-IN, FIRST-OUT MEMORY SCAS432 – JANUARY 1995DL PACKAGE• Operates at 3-V ..
SN74ALVC7806-40DL ,256 x 18 3.3-V asynchronous FIFO memory SN74ALVC7806 256 × 18LOW-POWER FIRST-IN, FIRST-OUT MEMORYSCAS591A – OCTOBER 1997 – REVISED APRIL 1 ..
SN74ALVCF162835GR ,3.3-V CMOS 18-Bit Universal Bus Driver with 3-State OutputsFEATURESDGG, DGV, OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 56NC GND ..
SN74ALVCF162835GR ,3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH162244 ,16-Bit Buffer/Driver With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1OE 1 48 2OE• EP ..
SN74ALVCH162244DGG ,16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTSFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1OE 1 48 2OE• EP ..
SN74LVC1G98DCKR E4 ,Configurable Multiple-Function Gate 6-SC70 -40 to 125 SCES417L–DECEMBER 2002–REVISED DECEMBER 2013Configurable Multiple-Function GateCheck for Samples: ..
SN74LVC1G98DCKRE4 ,Configurable Multiple-Function Gate 6-SC70 -40 to 125 SCES417L–DECEMBER 2002–REVISED DECEMBER 2013Logic ConfigurationsFigure 1. 2-to-1 Data Selector Wit ..
SN74LVC1G98DCKRG4 , CONFIGURABLE MULTIPLE-FUNCTION GATE
SN74LVC1G98DCKT ,Configurable Multiple-Function GateThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN74LVC1G98DRLR ,Configurable Multiple-Function Gate 6-SOT -40 to 125FEATURES DESCRIPTIONThis configurable multiple-function gate is designed2• Available in the Texas I ..
SN74LVC1G98YZPR ,Configurable Multiple-Function Gatefeatures configurable• Supports 5-V V OperationCCmultiple functions. The output state is determined ..
SN74ALVC7804-25DL
512 x 18 3.3-V asynchronous FIFO memory
Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-EmptyFlag Fast Access Times of 18 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously Data Rates From 0 to 40 MHz 3-State Outputs Pin Compatible With SN74ACT7804 Packaged in Shrink Small-Outline 300-mil
Package (DL) Using 25-mil Center-to-Center
Spacing
descriptionA FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ALVC7804 is
an 18-bit FIFO with high speed and fast access
times. Data is processed at rates up to 40 MHz
with access times of 18 ns in a bit-parallel format.
The SN74ALVC7804 is designed for 3-V to 3.6-VCC operation.
Data is written into memory on a low-to-high
transition of the load clock (LDCK) and is read out
on a low-to-high transition of the unload clock
(UNCK). The memory is full when the number of
words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect
on the data residing in memory. When the memory is empty, UNCK has no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-
full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory
is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output
is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable (PEN) is low.
The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE
flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.
A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,
and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power
up. The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
The data outputs are in the high-impedance state when the output-enable (OE) is high.
D16
D15
D14
D13
D12
D11
D10
VCC
GND
PEN
AF/AE
LDCK
FULL
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
GND
VCC
GND
UNCK
EMPTY
