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SN74ALVC16835TIN/a6avai18-Bit Universal Bus Driver With 3-State Outputs
SN74ALVC16835DGGRTIN/a16000avai18-Bit Universal Bus Driver With 3-State Outputs


SN74ALVC16835DGGR ,18-Bit Universal Bus Driver With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVC16835DGVR , 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74ALVC16835DGVR , 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
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SN74ALVC16835-SN74ALVC16835DGGR
18-Bit Universal Bus Driver With 3-State Outputs
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES125J–FEBRUARY 1998–REVISED NOVEMBER 2004 FEATURES DGG, DGV, OR DL PACKAGE • Member of the Texas Instruments Widebus™ (TOP VIEW) Family 1 56 NC GND • Operates From 1.65 V to 3.6 V NC 2 55 NC • Max t of 2 ns at 3.3 V pd Y1 3 54 A1 • ±24-mA Output Drive at 3.3 V 4 53 GND GND • Ideal for Use in PC100 Register DIMM, 5 52 Y2 A2 Revision 1.1 6 51 Y3 A3 • Latch-Up Performance Exceeds 250 mA Per 7 50 V V CC CC JESD 17 Y4 8 49 A4 • ESD Protection Exceeds JESD 22 Y5 9 48 A5 - 2000-V Human-Body Model (A114-A) Y6 10 47 A6 - 200-V Machine Model (A115-A) 11 46 GND GND - 1000-V Charged-Device Model (C101) 12 45 Y7 A7 13 44 Y8 A8 DESCRIPTION/ORDERING INFORMATION 14 43 Y9 A9 Y10 15 42 A10 This 18-bit universal bus driver is designed for 1.65-V Y11 16 41 A11 to 3.6-V V operation. CC 17 40 Y12 A12 Data flow from A to Y is controlled by the 18 39 GND GND output-enable (OE) input. The device operates in the 19 38 Y13 A13 transparent mode when the latch-enable (LE) input is 20 37 Y14 A14 high. The A data is latched if the clock (CLK) input is Y15 21 36 A15 held at a high or low logic level. If LE is low, the A V 22 35 V data is stored in the latch/flip-flop on the low-to-high CC CC Y16 23 34 A16 transition of CLK. When OE is high, the outputs are in the high-impedance state. 24 33 Y17 A17 25 32 GND GND To ensure the high-impedance state during power up 26 31 Y18 A18 or power down, OE should be tied to V through a CC 27 30 OE CLK pullup resistor; the minimum value of the resistor is LE 28 29 GND determined by the current-sinking capability of the driver. NC − No internal connection ORDERING INFORMATION (1) T PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING A Tube SN74ALVC16835DL SSOP - DL ALVC16835 Tape and reel SN74ALVC16835DLR TSSOP - DGG Tape and reel SN74ALVC16835DGGR ALVC16835 -40°C to 85°C TVSOP - DGV Tape and reel SN74ALVC16835DGVR VC835 VFBGA - GQL SN74ALVC16835GQLR Tape and reel VC835 VFBGA - ZQL (Pb-free) SN74ALVC16835ZQLR (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1998–2004, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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