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SN74ALS74A-SN74ALS74AD-SN74ALS74ADR-SN74ALS74AN-SN74ALS74ANSR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset
descriptionThese devices contain two independent
positive-edge-triggered D-type flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
The SN54ALS74A and SN54AS74A are
characterized for operation over the full military
temperature range of −55°C to 125°C. The
SN74ALS74A and SN74AS74A are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE The output levels in this configuration are not
specified to meet the minimum levels for VOH if the
lows at PRE and CLR are near VIL maximum.
Furthermore, this configuration is nonstable; that
is, it does not persist when PRE or CLR returns to
its inactive (high) level.
1CLK
1PRE
GND
2CLK
2PRE
SN54ALS74A, SN54AS74A... FK PACKAGE
(TOP VIEW)2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
NC − No internal connection
GND
