SN74ALS666DW ,Octal D-Type Transparent Read-Back Latches With 3-State Outputs SN74ALS666, SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A – ..
SN74ALS677ANT ,16-Bit Address Comparators 24-PDIP 0 to 70
SN74ALS678NT , 16-BIT ADDRESS COMAPARATORS
SN74ALS679N ,12-Bit Address Comparators
SN74ALS680N , 12-BIT ADDRESS COMPARATORS
SN74ALS688 ,8-Bit Identity Comparatorsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVC1G132DBVR ,Single 2-Input NAND Gate with Schmitt-Trigger InputFeatures 3 DescriptionThe SN74LVC1G132 device contains one 2-input1• Latch-Up Performance Exceeds 1 ..
SN74LVC1G132DCKR ,Single 2-Input NAND Gate with Schmitt-Trigger InputElectrical Characteristics....... 59.6 Glossary... 106.6 Switching Characteristics: –40°C to +85°C, ..
SN74LVC1G139DCUR ,2-Line-to-4-Line DecoderMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITSup ..
SN74LVC1G139DCUR ,2-Line-to-4-Line DecoderFeatures 3 DescriptionThis SN74LVC1G139 2-to-4 line decoder is designed1• Available in the Texas In ..
SN74LVC1G139DCUR ,2-Line-to-4-Line DecoderElectrical Characteristics....... 613.1 Documentation Support.... 136.6 Switching Characteristics.. ..
SN74LVC1G139YZPR ,2-Line-to-4-Line Decoder 8-DSBGA -40 to 85 SCES602E–AUGUST 2004–REVISED JANUARY 20185 Pin Configuration and FunctionsDCT PackageDCU Package8- ..
SN74ALS666DW
Octal D-Type Transparent Read-Back Latches With 3-State Outputs
Preset and Clear Inputs Package Options Include PlasticSmall-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
descriptionThese 8-bit D-type transparent latches are
designed specifically for storing the contents of
the input data bus, plus reading back the stored
data onto the input data bus. In addition, they
provide a 3-state buffer-type output and are easily
utilized in bus-structured applications.
While the latch enable (LE) is high, the Q outputs
of the SN74ALS666 follow the data (D) inputs. The
Q outputs of the SN74ALS667 provide the inverse
of the data applied to its D inputs. The Q or
Q output of both devices is in the high-impedance
state if either output-enable (OE1 or OE2) input is
at a high logic level.
Read back is provided through the read-back
control (OERB) input. When OERB is taken low,
the data present at the output of the data latches
passes back onto the input data bus. When OERB
is taken high, the output of the data latches is
isolated from the D inputs. OERB does not affect
the internal operation of the latches; however,
caution should be exercised to avoid a bus
conflict.
The SN74ALS666 and SN74ALS667 are
characterized for operation from 0°C to 70°C.
CLR
GND
PRE
SN74ALS667... DW OR NT PACKAGE
(TOP VIEW)OERB
OE1
CLR
GNDCC
OE2
PRE
