SN74ALS652ADWR ,Octal Bus Transceivers/Registers With 3-State Outputs SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN7 ..
SN74ALS653DW ,Octal Bus Transceivers/Registers With 3-State Outputs SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN7 ..
SN74ALS666DW ,Octal D-Type Transparent Read-Back Latches With 3-State Outputs SN74ALS666, SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A – ..
SN74ALS677ANT ,16-Bit Address Comparators 24-PDIP 0 to 70
SN74ALS678NT , 16-BIT ADDRESS COMAPARATORS
SN74ALS679N ,12-Bit Address Comparators
SN74LVC1G126DCK , SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC1G126DCK , SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC1G126DCKR ,Single Bus Buffer Gate With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LVC1G126SCES224R ..
SN74LVC1G126YZPR ,Single Bus Buffer Gate With 3-State OutputsFeatures 2 Applications1• Available in the Texas Instruments • Cable Modem Termination SystemsNanoF ..
SN74LVC1G132DBVR ,Single 2-Input NAND Gate with Schmitt-Trigger InputFeatures 3 DescriptionThe SN74LVC1G132 device contains one 2-input1• Latch-Up Performance Exceeds 1 ..
SN74LVC1G132DCKR ,Single 2-Input NAND Gate with Schmitt-Trigger InputElectrical Characteristics....... 59.6 Glossary... 106.6 Switching Characteristics: –40°C to +85°C, ..
SN74ALS652ADW-SN74ALS652ADWR
Octal Bus Transceivers/Registers With 3-State Outputs
Choice of True or Inverting Data Paths Choice of 3-State or Open-CollectorOutputs to A Bus
descriptionThese devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low input level selects real-time data, and
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the octal bus
transceivers and registers
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the
recommended maximum IOL for the -1 versions is increased to 48 mA. There are no -1 versions of the
SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NC – No internal connection
SN54ALS’, SN54AS’... FK PACKAGE
(TOP VIEW)OEAB
GND
SBA
OEBA
OEBA
GNDB7B6
OEABSABCLKABNC
CLKBASAB
