SN74ALS259N ,Octal Addressable Latches SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994SN5 ..
SN74ALS273 ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clear SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER ..
SN74ALS273DW ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS273DWR ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearlogic diagram (positive logic)1D 2D 3D 4D 5D 6D 7D 8D3 4 7 8 13 14 17 1811CLK1D 1D 1D 1D 1D 1D 1D 1 ..
SN74ALS273N ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS273NSR ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74LVC08ADBR ,Quadruple 2-Input Positive-AND GateSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54LVC08A,SN74LVC08 ..
SN74LVC08ADBRG4 ,Quadruple 2-Input Positive-AND Gate 14-SSOP -40 to 125Sample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54LVC08A,SN74LVC08 ..
SN74LVC08ADR ,Quadruple 2-Input Positive-AND GateMaximum Ratings . 511 Power Supply Recommendations... 127.2 ESD Ratings........ 512 Layout.... 127. ..
SN74LVC08ADRG4 ,Quadruple 2-Input Positive-AND Gate 14-SOIC -40 to 125Maximum Ratings . 511 Power Supply Recommendations... 127.2 ESD Ratings........ 512 Layout.... 127. ..
SN74LVC08ADTG4 , QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74LVC08ANSR ,Quadruple 2-Input Positive-AND GateLogic Diagram, Each Gate(Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addre ..
SN74ALS259N
Octal Addressable Latches
Enable/Disable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes Package Options Include PlasticSmall-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
descriptionThese 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as shown in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the
address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the
level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address
and data inputs.
The SN54ALS259 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS259 is characterized for operation from 0°C to 70°C.
Function Tables
FUNCTIOND = the level at the data input.
QiO = the level of Qi (i = Q, 1, ...7 as appropriate) before the indicated
steady-state input conditions were established.
SN54ALS259... FK PACKAGE
(TOP VIEW)S0NCQ5
CLR
GND
NC − No internal connection
GND
