SN74ALS175DR ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings over operating free-air temperature range, SN54/74ALS174,†SN54/74ALS175 (unless oth ..
SN74ALS175DR ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175BHEX/QUA ..
SN74ALS175N ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS175NSR ,Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clearlogic diagrams (positive logic)’ALS174, ’AS174 ’ALS175, ’AS175B91CLKCLR19CLRCLK43 21D 1D1D 1D1Q21QC ..
SN74ALS191A ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74ALS191ADR ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74LV573 ,OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LV573A ,Octal Transparent D-Type Latches With 3-State OutputsSN54LV573A, SN74LV573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS411I − APRIL 1998 − R ..
SN74LV573ADBRG4 ,Octal Transparent D-Type Latches With 3-State Outputs 20-SSOP -40 to 85/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV573ADWR ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC1191Q21D1DTo Seven Other ChannelsPin numbers shown are for th ..
SN74LV573ANSR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV573APW ,Octal Transparent D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ALS175-SN74ALS175DR-SN74ALS175N-SN74ALS175NSR
Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear
Isolation From External Disturbances
(’AS Only)
SN54ALS175 ...J OR W PACKAGE
SN54AS175B ...J PACKAGE
SN74ALS175, SN74AS175B... D, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174 ...J OR W PACKAGE
SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D , N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174, SN54AS174... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
NC – No internal connection
CLR
GND
VCC
CLK
SN54ALS175... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
CLR
GNDCC
CLK
descriptionThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
