SN74ALS166 ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ALS166D ,Parallel-Load 8-Bit Serial Shift Registers SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000D, DB, OR ..
SN74ALS166N ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ALS166NSR ,Parallel-Load 8-Bit Serial Shift Registers SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000D, DB, OR ..
SN74ALS166NSR ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS169BDR ,4-Bit Synchronous Up/Down Binary Countersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74LV4066APWR ,Quadruple Bilateral Analog Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV4066APWRG4 ,Quadruple Bilateral Analog Switch 14-TSSOP -40 to 85logic diagram (positive logic)AVCCVCCBCOne of Four Switches†absolute
SN74LV4066ARGYR ,Quadruple Bilateral Analog Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV4066ARGYRG4 ,Quadruple Bilateral Analog Switch 14-VQFN -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV540ADB , OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LV540ADBR ,Octal Buffers/Drivers With 3-State Outputs SCLS409I–MAY 1998–REVISED DECEMBER 20146 Pin Configuration and FunctionsSN74LV540A . . . RGY PACKA ..
SN74ALS166-SN74ALS166D-SN74ALS166N-SN74ALS166NSR
Parallel-Load 8-Bit Serial Shift Registers
Small-Outline (D) and Shrink Small-Outline
(DB) Packages and Standard Plastic (N) DIP
descriptionThe SN74ALS166 parallel-load 8-bit shift register
is compatible with most other TTL logic families.
All inputs are buffered to lower the drive
requirements. Input clamping diodes minimize
switching transients and simplify system design.
These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They
feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in
modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input
and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data
(A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial
data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a
two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the
system clock to be free running and the register can be stopped on command with the clock input. CLK INH
should be changed to the high level only when CLK is high. The buffered CLR overrides all other inputs, including
CLK, and sets all flip-flops to zero.
The SN74ALS166 is characterized for operation from 0°C to 70°C.
FUNCTION TABLEPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLK INH
CLK
GND
CLR
