SN74ALS165 ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS165N ,Parallel-Load 8-Bit Serial Shift Registers SDAS157B − JUNE 1982 − REVISED DECEMBER 1994SN54A ..
SN74ALS166 ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ALS166D ,Parallel-Load 8-Bit Serial Shift Registers SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000D, DB, OR ..
SN74ALS166N ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ALS166NSR ,Parallel-Load 8-Bit Serial Shift Registers SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000D, DB, OR ..
SN74LV4066APW ,Quadruple Bilateral Analog Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV4066APWR ,Quadruple Bilateral Analog Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV4066APWRG4 ,Quadruple Bilateral Analog Switch 14-TSSOP -40 to 85logic diagram (positive logic)AVCCVCCBCOne of Four Switches†absolute
SN74LV4066ARGYR ,Quadruple Bilateral Analog Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV4066ARGYRG4 ,Quadruple Bilateral Analog Switch 14-VQFN -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV540ADB , OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALS165-SN74ALS165N
Parallel-Load 8-Bit Serial Shift Registers
Package Options Include PlasticSmall-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
descriptionThe ′ALS165 are parallel-load 8-bit serial shift
registers that, when clocked, shift the data toward
serial (QH and QH ) outputs. Parallel-in access to
each stage is provided by eight individual direct
data (A−H) inputs that are enabled by a low level
at the shift/load (SH/LD) input. The ′ALS165 have
a clock-inhibit function and complemented serial
outputs.
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD is
held high and the clock inhibit (CLK INH) input is
held low. The functions of CLK and CLK INH are
interchangeable. Since a low CLK and a
low-to-high transition of CLK INH also
accomplishes clocking, CLK INH should be
changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD is held
high. The parallel inputs to the register are
enabled while SH/LD is low independently of the
levels of the CLK, CLK INH, or serial (SER) inputs.
The SN54ALS165 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS165 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE Shift = content of each internal register shifts
toward serial outputs. Data at SER is shifted
into first register.
SN54ALS165... FK PACKAGE
(TOP VIEW)CLKSH/LDNC
SER
CLK INH
GND
NC − No internal connection
GND
SERH
