SN74ALS164ANSR ,8-Bit Parallel-Out Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS165 ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS165N ,Parallel-Load 8-Bit Serial Shift Registers SDAS157B − JUNE 1982 − REVISED DECEMBER 1994SN54A ..
SN74ALS166 ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ALS166D ,Parallel-Load 8-Bit Serial Shift Registers SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000D, DB, OR ..
SN74ALS166N ,Parallel-Load 8-Bit Serial Shift Registersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV4066AN ,Quadruple Bilateral Analog Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV4066ANSR ,Quadruple Bilateral Analog Switchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV4066APW ,Quadruple Bilateral Analog Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV4066APWR ,Quadruple Bilateral Analog Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV4066APWRG4 ,Quadruple Bilateral Analog Switch 14-TSSOP -40 to 85logic diagram (positive logic)AVCCVCCBCOne of Four Switches†absolute
SN74LV4066ARGYR ,Quadruple Bilateral Analog Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ALS164A-SN74ALS164AD-SN74ALS164ADR-SN74ALS164AN-SN74ALS164ANSR
8-Bit Parallel-Out Serial Shift Registers
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
descriptionThis 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock; indicates a 1-bit shift.A
GNDG
CLR
CLK
