SN74ALS112ADR ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS112AN ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS113AD ,Dual J-K Negative-Edge-Triggered Flip-Flops With Preset 14-SOIC 0 to 70
SN74ALS113AN ,Dual J-K Negative-Edge-Triggered Flip-Flops With Preset 14-PDIP 0 to 70
SN74ALS11A ,Triple 3-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS11AD ,Triple 3-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV273A ,Octal D-Type Flip-Flops With ClearTable of Contents7.14 Typical Characteristics........ 91
SN74LV273ADB , OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN74LV273ADBR ,Octal D-Type Flip-Flops With ClearSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LV273ASCLS399K–A ..
SN74LV273ADBRG4 ,Octal D-Type Flip-Flops With Clear 20-SSOP -40 to 125Electrical Characteristics....... 712.1 Layout Guidelines.... 147.6 Timing Requirements, V = 2.5 V ..
SN74LV273ADBRG4 ,Octal D-Type Flip-Flops With Clear 20-SSOP -40 to 125Table of Contents7.14 Typical Characteristics........ 91
SN74LV273ADGVR ,Octal D-Type Flip-Flops With ClearFeatures 2 Applications1• 2-V to 5.5-V V Operation • Power Sub-station ControlsCC• Max t of 10.5 ns ..
SN74ALS112A-SN74ALS112ADR-SN74ALS112AN
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
Ceramic (J) 300-mil DIPs
descriptionThese devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements is transferred to the
outputs on the negative-going edge of the clock
pulse (CLK). Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
clock pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
The SN54ALS112A is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ALS112A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop) The output levels in this configuration may not meet the
minimum levels for VOH. Furthermore, this configuration is
nonstable; that is, it does not persist when either PRE or
CLR returns to its inactive (high) level.
SN54ALS112A... FK PACKAGE
(TOP VIEW)NC − No internal connection
1PRE
GND
2CLR
2CLK
2PRE
2CLR
2CLK
1PRE
1CLK1CLR
GND
2PRE NC