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SN74ALS109AD-SN74ALS109AN
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset
descriptionThese devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE The output levels in this configuration are not specified to
meet the minimum levels for VOH if the lows at PRE and
CLR are near VIL maximum. Furthermore, this
configuration is nonstable; that is, it does not persist when
either PRE or CLR returns to its inactive (high) level.
SN54ALS109A, SN54AS109A...FK PACKAGE
(TOP VIEW)NC − No internal connection
1CLK
1PRE
GND
2CLK
2PRE
2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
