SN74AHCT374DWR ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AHCT374NSR , OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374PW ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74AHCT374PWR ,Octal D-type Edge-Triggered Flip-Flops With 3-State OutputsSN54AHCT374, SN74AHCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCLS241L – OCTOB ..
SN74AHCT540DBR ,Octal Buffers/Drivers With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)1OE119OE22 18A1 Y1ToSevenOtherChannelsABSOLUTE
SN74AHCT540DW ,Octal Buffers/Drivers With 3-State OutputsSN54AHCT540SN74AHCT540
SN74LV10ANSR ,Triple 3-Input Positive-NAND Gatemaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV10APWR ,Triple 3-Input Positive-NAND Gatemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV11ADGVR ,Triple 3-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV11APW ,Triple 3-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV11APWR ,Triple 3-Input Positive-AND Gates SCES345D − DECEMBER 2000 − REVISED APRIL 2005SN54LV ..
SN74LV11ATPWRG4Q1 ,Automotive Catalog Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 105maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AHCT374-SN74AHCT374DW-SN74AHCT374DWR-SN74AHCT374PW-SN74AHCT374PWR
Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs
description/ordering informationThe ’AHCT374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
