SN74AHCT174NSR ,Hex D-Type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AHCT174PWR ,Hex D-Type Flip-Flops With Clear SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPSWITH CLEARSCLS419F – JUNE 1998 – REVISED APRIL 2002S ..
SN74AHCT1G00 ,Single 2-Input Positive-NAND GateElectrical Characteristics....... 412 Device and Documentation Support........ 116.6 Switching Char ..
SN74AHCT1G00DBVR ,Single 2-Input Positive-NAND GateMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74AHCT1G00DCKR ,Single 2-Input Positive-NAND GateMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do no ..
SN74AHCT1G02DBVR ,Single 2-Input Positive-NOR Gatemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS91N ,8-BIT SHIFT REGISTERS
SN74LS92D ,DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
SN74LS92D ,DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTERLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS931 14CP CP1 0J Q J Q J Q J Q2 13NC14 MR1CP0 CP CP ..
SN74LS92N ,DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTERSN54/74LS90SN54/74LS92DECADE COUNTER;SN54/74LS93DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTERDECADE ..
SN74LS92NSR ,Divide-By-Twelve Decade Counter
SN74LS92NSR ,Divide-By-Twelve Decade Counter
SN74AHCT174N-SN74AHCT174NSR-SN74AHCT174PWR
Hex D-Type Flip-Flops With Clear
– Shift Registers
– Pattern Generators Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
descriptionThese positive-edge-triggered D-type flip-flops
have a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
SN54AHCT174... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
GND
CLK
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
