SN74AHCT125DGVR ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)11OE2 31A 1Y42OE5 62A 2Y103OE9 83A 3Y134OE11124A 4YPin numbers shown ..
SN74AHCT125DR ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)11OE2 31A 1Y42OE5 62A 2Y103OE9 83A 3Y134OE11124A 4YPin numbers shown ..
SN74AHCT125DRG4 ,Quadruple Bus Buffer Gates With 3-State Outputs 14-SOIC -40 to 85 SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATESWITH 3-STATE OUTPUTSSCLS264O − DECEMBER 1995 − ..
SN74AHCT125N ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AHCT125NSR ,Quadruple Bus Buffer Gates With 3-State Outputs SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATESWITH 3-STATE OUTPUTSSCLS264O − DECEMBER 1995 − ..
SN74AHCT125PW ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS74AN ,LOW POWER SCHOTTKYq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74ANSR ,Dual D-type pos.-edge-triggered flip-flops with preset and clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS75N ,4-BIT D LATCHSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
SN74LS75NSR ,Quad bistable latches
SN74LS75NSR ,Quad bistable latches
SN74AHCT125D-SN74AHCT125DBLE-SN74AHCT125DBR-SN74AHCT125DGVR-SN74AHCT125DR-SN74AHCT125DRG4-SN74AHCT125N-SN74AHCT125NSR-SN74AHCT125PW-SN74AHCT125PWLE-SN74AHCT125PWR-SN74AHCT125PWRG4-SN74AHCT125RGYR
Quadruple Bus Buffer Gates With 3-State Outputs
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003
Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)1OE
2OE
GND
VCC
4OE
3OE
SN54AHCT125 ...J OR W PACKAGE
SN74AHCT125 ...D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)12019
91011 1213
3OE
2OE1OENC3A4OE
GND
SN54AHCT125... FK PACKAGE
(TOP VIEW)NC − No internal connection
SN74AHCT125... RGY PACKAGE
(TOP VIEW)4OE
3OE
2OE
1OE
GND
description/ordering informationThe ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
