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Home ›  SS55 > SN74AHC74-SN74AHC74D-SN74AHC74DBLE-SN74AHC74DBR-SN74AHC74DGVR-SN74AHC74DR-SN74AHC74N-SN74AHC74NSR-SN74AHC74PW-SN74AHC74PWLE-SN74AHC74PWR-SN74AHC74PWRG4-SN74AHC74RGYR,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
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Partno Mfg Dc Qty AvailableDescript
SN74AHC74TIN/a67avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74DTIN/a1030avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74DBLETIN/a1553avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74DBRTIN/a2920avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74DGVRTIN/a3255avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74DRTI ?N/a24870avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74NTIN/a5000avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74NSRTIN/a367avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74PWTI ?N/a100avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74PWTIN/a851avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74PWLETIN/a4000avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74PWRTEXASN/a400avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN74AHC74PWRG4TIN/a775avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 125
SN74AHC74RGYRTEXAS&BBN/a2avaiDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset


SN74AHC74DR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
SN74AHC74N ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetFEATURES DESCRIPTIONThe ’AHC74 dual positive-edge-triggered devices are• Operating Range 2-V to 5.5 ..
SN74AHC74NSR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN74AHC74PW ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN74AHC74PW ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)UNITSupply volt ..
SN74AHC74PWLE ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset SCLS255K–DECEMBER 1995–REVISED DECEMBER 2013Dual Positive-Edge-Triggered D-Type Flip-Flops With Cl ..
SN74LS682J , 8-BIT MAGNITUDE/IDENTITTY COMPARATORS
SN74LS683N , 8-BIT MAGNITUDE/IDENTITTY COMPARATORS
SN74LS685N , 8-BIT MAGNITUDE/IDENTITY COMPARATORS
SN74LS685N , 8-BIT MAGNITUDE/IDENTITY COMPARATORS
SN74LS688NSR ,8-Bit Magnitude/Identity Comparators
SN74LS689N , 8-BIT MAGNITUDE/IDENTITTY COMPARATORS


SN74AHC74-SN74AHC74D-SN74AHC74DBLE-SN74AHC74DBR-SN74AHC74DGVR-SN74AHC74DR-SN74AHC74N-SN74AHC74NSR-SN74AHC74PW-SN74AHC74PWLE-SN74AHC74PWR-SN74AHC74PWRG4-SN74AHC74RGYR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
SN54AHC74, SN74AHC74 www.ti.com SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Check for Samples: SN54AHC74, SN74AHC74 1FEATURES DESCRIPTION The ’AHC74 dual positive-edge-triggered devices are • Operating Range 2-V to 5.5-V V CC D-type flip-flops. • Latch-Up Performance Exceeds 250 mA Per A low level at the preset (PRE) or clear (CLR) inputs JESD 17 sets or resets the outputs, regardless of the levels of • ESD Protection Exceeds JESD 22 the other inputs. When PRE and CLR are inactive – 2000-V Human-Body Model (A114-A) (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the – 200-V Machine Model (A115-A) positive-going edge of the clock pulse. Clock – 1000-V Charged-Device Model (C101) triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1995–2013, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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