SN74AHC174D ,Hex D-Type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AHC174DBR ,Hex D-Type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AHC174DR ,Hex D-Type Flip-Flops With Clear/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74AHC174PWR ,Hex D-Type Flip-Flops With Clear SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPSWITH CLEARSCLS425F – JUNE 1998 – REVISED FEBRUARY 2002 ..
SN74AHC1G00DBVR ,Single 2-Input Positive-NAND GateTable of Contents8.2 Functional
SN74AHC1G00DBVRG4 ,Single 2-Input Positive-NAND Gate 5-SOT-23 -40 to 125Electrical Characteristics....... 512.1 Documentation Support ... 136.6 Switching Characteristics: ..
SN74LS368N ,3-STATE HEX BUFFERSSN54/74LS365ASN54/74LS366ASN54/74LS367A3-STATE HEX BUFFERSSN54/74LS368AThese devices are high speed ..
SN74LS37 ,Quad 2-input positive-NAND buffers
SN74LS373 ,Octal Transparent Latch/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS373DW ,OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRA ..
SN74LS373DWR ,Octal D-type Transparent Latches with 3-state Outputs/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS373DWR2 ,Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
SN74AHC174D-SN74AHC174DBR-SN74AHC174DR-SN74AHC174PWR
Hex D-Type Flip-Flops With Clear
– Shift Registers
– Pattern Generators Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
descriptionThe ’AHC174 devices are positive-edge-triggered
D-type flip-flops with a direct clear (CLR) input and
are designed for 2-V to 5.5-V VCC operation.
Information at the data (D) inputs that meets the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
SN54AHC174... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
GND
CLK
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
