SN74AHC125DR ,Quadruple Bus Buffer Gates With 3-State OutputsMaximum Ratings.. 511 Layout.... 156.2 ESD Ratings........ 511.1 Layout Guidelines.... 156.3 Recomm ..
SN74AHC125MPWREP ,Enhanced Product Quadruple Bus Buffer Gates With 3-State Outputs 14-TSSOP -55 to 125SN74AHC125-EP QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTSSCLS485A – MAY 2003 – REVISED JUNE 2003D ..
SN74AHC125N ,Quadruple Bus Buffer Gates With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54AHC125,SN74AHC12 ..
SN74AHC125NSR ,Quadruple Bus Buffer Gates With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54AHC125,SN74AHC12 ..
SN74AHC125PW ,Quadruple Bus Buffer Gates With 3-State OutputsLogic Diagram (Positive Logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..
SN74AHC125PWLE ,Quadruple Bus Buffer Gates With 3-State OutputsElectrical Characteristics....... 612.1 Documentation Support.... 166.6 Switching Characteristics: ..
SN74LS32M ,Quad 2-Input OR Gate
SN74LS32MEL ,Quad 2-Input OR Gate
SN74LS32MEL ,Quad 2-Input OR Gate
SN74LS32NE4 ,Quad 2-input positive-OR gates 14-PDIP 0 to 70
SN74LS33 ,Quad 2-input positive-NOR buffers with open collector outputs
SN74LS33DR ,Quad 2-input positive-NOR buffers with open collector outputs
SN74AHC125-SN74AHC125D-SN74AHC125DBR-SN74AHC125DR-SN74AHC125N-SN74AHC125NSR-SN74AHC125PW-SN74AHC125PWLE-SN74AHC125PWR-SN74AHC125PWRG4-SN74AHC125RGYR-SN74AHC125RGYRG4
Quadruple Bus Buffer Gates With 3-State Outputs
1OE1A 1Y3
2OE 2Y
3OE3A 3Y8
4OE 4YProduct
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SN54AHC125, SN74AHC125SCLS256L–DECEMBER 1995–REVISED NOVEMBER 2016
SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs Features Operating Range:2Vto 5.5V Latch-Up Performance Exceeds 250 mA Per
JESD17 Four Individual Output Enable Pins All Inputs Have Schmitt-Trigger Action
Applications Flow Meters Programmable Logic Controllers Power Over Ethernet (PoE) Motor Drives and Controls Electronic Point-of-Sale
DescriptionThe SNx4AHC125 devices are quadruple bus buffer
gates featuring independent line drivers with 3-state
outputs. Each outputis disabled when the associated
output-enable (OE) inputis high. When OEis low, the
respective gate passes the data from theA inputto
itsY output. ensure the high-impedance state during power up power down, OE must be tiedto VCC througha
pullup resistor; the minimum valueof the resistoris
determined by the current-sinking capability of the
driver.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)arefortheD, DB, DGV,J,N, NS, PW, RGY, andW packages.
