SN74AHC123ADR ,Dual Retriggerable Monostable Multivibratorsmaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
SN74AHC123ADRG4 ,Dual Retriggerable Monostable Multivibrators 16-SOIC -40 to 85logic diagram, each multivibrator (positive logic)R /Cext extA CextBQCLRR Qinput/output timing diag ..
SN74AHC123APWR ,Dual Retriggerable Monostable Multivibratorsmaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
SN74AHC125 ,Quadruple Bus Buffer Gates With 3-State OutputsFeatures... 18.3 Feature Description.... 122 Applications..... 18.4 Device Functional Modes.... 123 ..
SN74AHC125D ,Quadruple Bus Buffer Gates With 3-State Outputs SCLS256L–DECEMBER 1995–REVISED NOVEMBER 20165 Pin Configuration and FunctionsD, DB, DGV, N, NS, J, ..
SN74AHC125D ,Quadruple Bus Buffer Gates With 3-State OutputsFeatures... 18.3 Feature Description.... 122 Applications..... 18.4 Device Functional Modes.... 123 ..
SN74LS32M ,Quad 2-Input OR Gate
SN74LS32MEL ,Quad 2-Input OR Gate
SN74LS32MEL ,Quad 2-Input OR Gate
SN74LS32NE4 ,Quad 2-input positive-OR gates 14-PDIP 0 to 70
SN74LS33 ,Quad 2-input positive-NOR buffers with open collector outputs
SN74LS33DR ,Quad 2-input positive-NOR buffers with open collector outputs
SN74AHC123ADBR-SN74AHC123ADG4-SN74AHC123ADR-SN74AHC123ADRG4-SN74AHC123APWR
Dual Retriggerable Monostable Multivibrators
Retriggerable for Very Long Output Pulses Overriding Clear Terminates Output Pulse Glitch-Free Power-Up Reset On Outputs Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering informationThe ’AHC123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
5.5-V VCC operation.
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low, and the B input
goes high. In the second method, the B input is
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
