SN74ACT7806-20DL ,256 x 18 asynchronous FIFO memory SN74ACT7806 256 × 18STROBED FIRST-IN, FIRST-OUT MEMORYSCAS438C – APRIL 1992 – REVISED APRIL 1998DL ..
SN74ACT7806-40DL ,256 x 18 asynchronous FIFO memory SN74ACT7806 256 × 18STROBED FIRST-IN, FIRST-OUT MEMORYSCAS438C – APRIL 1992 – REVISED APRIL 1998DL ..
SN74ACT7806-40DLR , 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7808-25FN ,2048 X 9 asynchronous FIFO memory SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBE ..
SN74ACT7808-40FN ,2048 X 9 asynchronous FIFO memory SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBE ..
SN74ACT7813-15DL ,64 x 18 synchronous FIFO memory SN74ACT7813 64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 199 ..
SN74LS27DR ,Triple 3-input positive-NOR gates
SN74LS28 ,QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280N ,9-BIT ODD/EVEN PARITY GENERATORS/CHECKERSSN54/74LS2809-BIT ODD/EVEN PARITYGENERATORS/CHECKERSThe SN54/74LS280 is a Universal 9-Bit Parity Ge ..
SN74ACT7806-20DL-SN74ACT7806-40DL
256 x 18 asynchronous FIFO memory
Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-EmptyFlag Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously Data Rates up to 50 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804
and SN74ACT7814 Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
descriptionA FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7806 is a
256-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.
Data is written into memory on a low-to-high
transition at the load clock (LDCK) input and is
read out on a low-to-high transition at the unload
clock (UNCK) input. The memory is full when the
number of words clocked in exceeds the number
of words clocked out by 256. When the memory is
full, LDCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The
first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value
(X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO
contains X or fewer words or (256 – Y) or more words. The AF/AE flag is low when the FIFO contains between
(X + 1) and (255 – Y) words.
D16
D15
D14
D13
D12
D11
D10
VCC
GND
PEN
AF/AE
LDCK
FULL
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
GND
VCC
GND
UNCK
EMPTY
NC – No internal connection
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