SN74ACT74D ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT74DBR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ACT74DR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ACT74NSR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ACT74PW ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ACT74PWR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetlogic diagram, each flip-flop (positive logic)PRECLK CCCQTGC C CCD TG TG TGQC C CCLR2POST OFFICE BO ..
SN74LS273M ,Octal D Flip-Flop with Clear3SN74LS273AC WAVEFORMS1/f maxtWtMRW1.3 VCP 1.3 V 1.3 V t1.3 V 1.3 Vrec1.3 Vt (H) t (L)s s CPt (H) t ..
SN74LS273N ,OCTAL D FLIP-FLOP WITH CLEARSN54/74LS273OCTAL D FLIP-FLOP WITH CLEARThe SN54/ 74LS273 is a high-speed 8-Bit Register. The regis ..
SN74LS273NSR ,Octal D-Type Flip-Flops With Clear SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – ..
SN74LS279A ,Quad /S-/R latches
SN74LS279AN ,Quad /S-/R latches
SN74LS27DR ,Triple 3-input positive-NOR gates
SN74ACT74D-SN74ACT74DBR-SN74ACT74DR-SN74ACT74NSR-SN74ACT74PW-SN74ACT74PWR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
1CLR
1CLK
1PRE
GNDCC
2CLR
2CLK
2PRE
2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
(TOP VIEW)NC − No internal connection
description/ordering informationThe ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at D can be changed without affecting the levels at the outputs.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
