SN74ACT534DW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ACT534DWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SN54ACT534, SN74ACT534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS556C – NOVEMB ..
SN74ACT534PWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ACT564DWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT564DWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS549B – NOVEMB ..
SN74ACT573DW ,Octal D-Type Transparent Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC1 191Q21D 1DTo Seven Other Channels†absolute
SN74LS259BDR ,Octal addressable latches
SN74LS259ML1 ,8-Bit Addressable LatchFUNCTIONAL DESCRIPTIONThe SN74LS259 has four modes of operation as shown in other inputs in the LOW ..
SN74LS259MR1 ,8-Bit Addressable Latch3SN74LS259DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)LimitsSym ..
SN74LS259N ,8-Bit Adder LatchSN54/74LS2598-BIT ADDRESSABLE LATCHThe SN54/ 74LS259 is a high-speed 8-Bit Addressable Latch design ..
SN74LS26 ,Quad 2-input high-voltage interface positive-NAND gateslogic diagramY23NC - No internal connection1YY4Y1,=Dy-----"ICC)-2B',1CCC)r------3BICC)-----43positi ..
SN74LS260DR2 ,Dual 5-Input NOR Gate
SN74ACT534DBR-SN74ACT534DW-SN74ACT534DWR-SN74ACT534PWR
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
3-State Inverting Outputs Drive Bus LinesDirectly Full Parallel Access for Loading
description/ordering informationThese octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. The devices are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complements of the
logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
CLK
SN54ACT534... FK PACKAGE
(TOP VIEW)1QOE
GND
CLK
