SN74ACT374NSR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ACT374NSR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State OutputsSN54ACT374, SN74ACT374OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS539F − OCTOBER ..
SN74ACT374PW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE11CLKC121Q31D1DTo Seven Other Channels†absolute
SN74ACT374PWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT533DW ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT533PWR ,Octal Transparent D-Type Latches With 3-State Outputs SN54ACT533, SN74ACT533 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS553C – NOVEMBER 199 ..
SN74LS259 ,8-Bit Adder Latchcommon Clear for resetting all latches, as well as, an active LOWEnable.LOW• Serial-to-Parallel Con ..
SN74LS259 ,8-Bit Adder LatchFUNCTIONAL DESCRIPTIONThe SN74LS259 has four modes of operation as shown in other inputs in the LOW ..
SN74LS259B ,Octal addressable latches
SN74LS259B ,Octal addressable latches
SN74LS259BDR ,Octal addressable latches
SN74LS259ML1 ,8-Bit Addressable LatchFUNCTIONAL DESCRIPTIONThe SN74LS259 has four modes of operation as shown in other inputs in the LOW ..
SN74ACT374DBR-SN74ACT374DW-SN74ACT374NSR-SN74ACT374PW-SN74ACT374PWR
Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 10 ns at 5 V Inputs Are TTL-Voltage Compatible
description/ordering informationThese 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
VCC
CLK
SN54ACT374 ...J OR W PACKAGE
SN74ACT374... DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)21 201910111213
SN54ACT374...FK PACKAGE
(TOP VIEW)1QOE
GND
CLK
